As ASIC devices become more integrated, it has become increasingly difficult to debug new devices, particularly during initial debug testing. Historically, a logic analyzer is used to extract state information from a system to assist in initial debug testing, but due to the large level of integration now used in ASIC design, some of the pertinent state information is buried deep in the chip logic, and is difficult to access with logic analyzers and conventional test equipment.
One solution to this problem is to include dedicated test pins on an ASIC or other device to be tested so that internal state information can be provided on these external pins. However, this solution may be less than optimal because these pins would only be used during debug testing, and rarely (if ever) used again once the device is debugged. Thus, there exists a need for an efficient and cost-effective method for providing internal state information or other diagnostic information for integrated devices such as ASICs.